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1/16 september 2013 1 - introduction the st10f269 is a new derivative of the stmicroelectronics st10 family of 16-bit single-chip cmos micro-controllers. it is upward compatible with the st10f168. the goal of this document is to enlighten the differences between the st10f269 and st10f168 and is intended for hardware or software designers who are adapting an existing application based on the st10f168 to the st10f269. this document will present the modified functionalities of the st10f269, then the new ones before looking at the modified and the new registers. for each part, the differences with the st10f168 that may be impacting will be stressed and some advice on the way they can be handled will be given. AN1313 application note porting an application from the st10f168 to the st10f269 by charles aubenas docid7589 rev 2
AN1313 - application note 2/16 1 introduction ......................................................................................................... 1 2 modified functionalities.................................................................................. 4 2.1 pin out ..................................................................................................................... . 4 2.1.1 pin 84 .......................................................................................................................... 4 2.1.1.1 hardware impact ......................................................................................................... 4 2.1.1.2 software impact........................................................................................................... 4 2.1.2 pins 17 and 56............................................................................................................ . 4 2.1.2.1 hardware impact ......................................................................................................... 4 2.1.2.2 software impact........................................................................................................... 4 2.2 xram .......................................................................................................................... 4 2.2.1 hardware impact ......................................................................................................... 4 2.2.2 software impacts......................................................................................................... 4 2.3 flash eeprom ........................................................................................................ 5 2.3.1 hardware impacts ....................................................................................................... 5 2.3.2 software impacts......................................................................................................... 5 2.4 a/d converter ....................................................................................................... 7 2.4.1 hardware impacts ....................................................................................................... 7 2.4.2 software impacts......................................................................................................... 7 3 new functionnalities ........................................................................................ 8 3.1 can modules .......................................................................................................... 8 3.1.1 hardware impacts ....................................................................................................... 8 3.1.2 software impacts......................................................................................................... 8 3.2 real time clock .................................................................................................... 8 3.2.1 hardware impacts ....................................................................................................... 8 3.2.2 software impacts......................................................................................................... 8 3.3 mac unit ................................................................................................................... 8 3.3.1 hardware impacts ....................................................................................................... 8 3.3.2 software impacts......................................................................................................... 8 4 modified registers ............................................................................................. 9 4.1 picon register...................................................................................................... 9 4.1.1 hardware impacts ....................................................................................................... 9 4.1.2 software impacts......................................................................................................... 9 4.2 wdtcon register ................................................................................................. 10 4.2.1 hardware impacts ....................................................................................................... 10 4.2.2 software impacts......................................................................................................... 10 5 new registers ...................................................................................................... 11 5.1 new registers impacting the application ................................................ 11 5.1.1 xpercon register .................................................................................................... 11 5.1.1.1 hardware impacts ....................................................................................................... 12 5.1.1.2 software impacts........................................................................................................ .12 table contents page
AN1313 - application note 3/16 5.1.2 poconx registers ..................................................................................................... 12 5.1.2.1 hardware impacts ....................................................................................................... 12 5.1.2.2 software impacts........................................................................................................ .13 5.2 new registers not impacting the application........................................ 13 5.2.1 odp4 register (f1ca h / e5 h ) ...................................................................................... 13 5.2.2 exisel register (f1da h / da h )................................................................................... 13 6 electrical characteristics .......................................................................... 14 6.1 dc characteristics ............................................................................................ 14 6.1.1 absolute maximum ratings......................................................................................... 14 6.1.2 dc characteristics....................................................................................................... 14 6.1.2.1 operating voltage....................................................................................................... .14 6.1.2.2 programming voltage.................................................................................................. 14 6.1.2.3 miscellaneous ........................................................................................................... 14 6.2 ac characteristics at 25mhz .......................................................................... 14 6.2.1 hardware impact ......................................................................................................... 14 6.2.2 software impact........................................................................................................... 14 7 references ............................................................................................................ 15
AN1313 - application note 4/16 2 - modified functionalities 2.1 - pin out 2.1.1 - pin 84 this pin was named vpp/rpd on the st10f168 and was the 12v input pin for flash programming. in the st10f269, it is now only used as rpd as the flash is a single voltage one. 2.1.1.1 - hardware impact this pin is no longer designed to accept 12v inputs. its ratings are the same as any other pin: -0.5v to vdd +0.5v. 2.1.1.2 - software impact none. note: some applications migth be using the vpp pin as a protection for flash programming by software controlling the 12v charge pump. the st10f269 being now a single voltage flash, vpp will appear as permanently on and thus such a protection can not be reproduced with the st10f269. 2.1.2 - pins 17 and 56 for the st10f168, these are v dd pins connected to 5volts. for the st10f269, these pins 17 and 56 are de-coupling pins for the 3,3v and respectively named dc2 and dc1. a de-coupling capacitor must be connected to these pins and the nearest v ss . 2.1.2.1 - hardware impact the application board should be re-designed in order to introduce the decoupling capacitors. 2.1.2.2 - software impact none. 2.2 - xram the st10f168 has only 6kbytes of extension ram while the st10f269 has 10kbytes. the xram address range in the st10f168 is 00d000h - 00e7ffh and is enabled if xpen (bit 2 of syscon register) is set. the xram of the st10f269 is divided into 2 ranges named xram1 of 2kbytes and xram2 of 8kbytes: C the xram1 address range is 00e000h - 00e7ffh if enabled ( xpen set -bit 2 of syscon register- and xram1en set - bit 2 of xpercon register-). C the xram2 address range is 00c000h - 00dfffh if enabled (xpen set -bit 2 of syscon register- and xram2en set - bit 3 of xpercon register-). 2.2.1 - hardware impact none. 2.2.2 - software impacts the memory mapping of the application may be impacted by the difference in xram size or by the separation in 2 ranges independently selectable. in the st10f168, setting xpen bit in syscon register enables the xram. in the st10f269, setting xpen bit in syscon register enables the xram1 only (default reset configuration of the new xpercon register). thus accesses to the range 00d000h - 00dfffh that was part of the st10f168 xram will be redirected to external memory. three configurations may be seen: 1. configuration 1: no external memory in address range 00c000h - 00cfffh. impact: one register to configure. work-around: set the bit xram2en of xpercon new register. it enables the second xram range. the total xram range is then 00c000h - 00e7ffh which includes the st10f168 range.
AN1313 - application note 5/16 2. configuration 2: external memory exists in page 3 and is below 2k byte size. impact: one register to configure, the external memory has to be remapped within page 3. work-around: set the bit xram2en and clear the bit xram1en of xpercon new register. then remap your variables to uses the xram2 range as your xram (bigger than the st10f168 so no issue) and remap your 2k byte range of external memory at the xram1 location. this way you keep everything within page 3. 3. configuration 3: external memory exists in page 3 and is above 2k byte size. impact: one register to configure, the external memory to be remapped in another page. work-around: set the bit xram2en of the xpercon new register and relocate your external memory in page 2 (address range 0x8000 - 0xbfff) if possible. then change the link directives according to the new mapping. note: the setting of the bits in xpercon must be done before enabling the xbus peripherals by the xpen bit of syscon. 2.3 - flash eeprom the st10f168 and the st10f269 dont have the same flash memories. the embedded flash of the st10f269 has a technology really similar to the stand-alone flash memories of stmicroelectronics. 2.3.1 - hardware impacts the 12 volts input on pin 84 is no longer needed. 2.3.2 - software impacts the mapping of the application and the programming and erasing routines are impacted. st10f168 bank 0: this range is fully compatible with the block 0 of the st10f269. st10f168 bank 1: this range is now covered by the blocks 1, 2 and 3 of the st10f269. it is not mandatory to re-map code and data: these 3 blocks could be considered as a single range. st10f168 bank 2 and bank 3: the highest third of bank 2 and the lowest third of bank 3 correspond to the block 5 of the st10f269. code and data have to be remapped to take care of this separation in three ranges of 64k bytes if these banks were likely to be independently reprogrammed. the programming-erasing software must also be rewritten as the st10f269 does not work with the steak tm but with a write/erase controller. table 1 : flash memories key characteristics st10f168 st10f269 flash size 256k bytes 256k bytes flash organization 4 banks 7 blocks programming voltage 12 volts 5 volts programming method steak tm write/erase controller program/erase cycles 10 000, 20 years of data retention 100.000, 3 10 years of data retention
AN1313 - application note 6/16 figure 1 : flash memories mapping note: bank 0 (block 0) and bank 1l (block 1) may be remapped from segment 0 to segment 1 by setting syscon-roms1 (before einit). segment 4 13 12 11 10 segment 3 0f 0e 0d 0c segment 2 0b 0a 09 08 segment 1 07 06 05 04 segment 0 03 02 1 00 st10f168 flash mapping 04ffff 04c000 048000 044000 040000 038000 bank 3: 96k bytes 037fff 034000 030000 02c000 028000 024000 020000 bank 2: 96k bytes 01ffff 01c000 018000 bank 1h: 32k bytes 017fff 014000 bank 1l (*) : 16k bytes 013fff 010000 bank 0 (*) : 16k bytes 00ffff 008000 007fff 004000 bank 1l (*) : 16k bytes 003fff 000000 bank 0 (*) : 16k bytes st10f269 flash mapping 04ffff 04c000 048000 044000 040000 block 6: 64k bytes 03ffff 038000 034000 030000 block 5: 64k bytes 02ffff 02c000 028000 024000 020000 block 4: 64k bytes 01ffff 01c000 018000 block 3: 32k bytes 017fff 016000 block 2 (*) : 8k bytes 015fff 014000 block 1 (*) : 8k bytes 013fff 010000 block 0 (*) : 16k bytes 00ffff 008000 007fff 006000 block 2 (*) : 8k bytes 005fff 004000 block 1 (*) : 8k bytes 003fff 000000 block 0 (*) : 16k bytes
AN1313 - application note 7/16 2.4 - a/d converter the a/d converter of the st10f269 is based upon a resistor-capacitor circuitry while the st10f168 one is based upon fully switched capacitors. the st10f269 does not have the self-calibrated feature, but the guaranteed total unadjusted error is 2 lsb. 2.4.1 - hardware impacts the table below lists the differences in the dc characteristics of the two devices. 2.4.2 - software impacts none. table 2 : adc differences parameter symbol limit values for st10f168 limit values for st10f269 unit minimum maximum minimum maximum analog reference voltage v aref 4.0 v dd + 0.1 4.0 v dd + 0.1 v analog input voltage v ain v agnd v aref v agnd v aref v adc input capacitance not sampling sampling c ain - - 33 33 - - 10 15 pf pf sample time t s -2 t sc 2 t cc 16 t cc conversion time t c -1 4 t cc + t s + 4 tcl - 14 t cc + t s + 4 tcl total unadjusted error tue -2.0 +2.0 -2.0 +2.0 lsb internal resistance of analog source r asrc -t s [ns]/330 - 0.25 t s [ns]/150 - 0.25 k w reference supply current running mode power-down mode i aref - - 500 1 a a differential nonlinearity dnl -0.5 +0.5 lsb integral nonlinearity inl -1.5 +1.5 lsb offset error ofs -1.0 +1.0 lsb
AN1313 - application note 8/16 3 - new functionnalities 3.1 - can modules the st10f168 has only one can module. the st10f269 has two can modules which are both identical to the one of the st10f168. by default none of the can modules is enabled. the two modules can be independently enabled or disabled during the initialization phase. 3.1.1 - hardware impacts none. 3.1.2 - software impacts none. 3.2 - real time clock this is a new functionality of the st10f269. the real time clock is an independent timer. its clock is directly derived from the clock oscillator so that it can keep on running even in idle or power down mode (if enabled to). 3.2.1 - hardware impacts none. 3.2.2 - software impacts none. by default this peripheral is disabled. 3.3 - mac unit this multiply and accumulate unit is a feature added on the st10f269. it provides dsp-like instructions that may be valuable for signal processing algorithms. 3.3.1 - hardware impacts none. 3.3.2 - software impacts none.
AN1313 - application note 9/16 4 - modified registers 4.1 - picon register some bits have been added, and some suppressed in this register for the st10f269. the port input control register picon is used to select between ttl and cmos-like input thresholds. the cmos-like input thresholds are defined above the ttl levels and feature a defined hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds. in the st10f168, these functionality is available for all pins of port 2, port 3, port 7 and port 8. in the st10f269, this functionality has been added for the pins of port 4. it is also used to select the output driver characteristics of some pins of the st10f168 but no longer on the st10f269 where the poconx registers have been added for this purpose (see new registers section). st10f168: picon (f1c4h / e2h) esfr reset value: 0000h st10f269: picon (f1c4h / e2h) esfr reset value: 0000h 4.1.1 - hardware impacts none. 4.1.2 - software impacts the initialization of the picon register is impacted. moreover some other registers will have to be configured. the initialization of the output driver characteristic has to be done through the pocon registers and the high byte of the picon register is reserved on the st10f269. check that the st10f168 software was not writing in bit4 of picon which is no longer reserved on the st10f269. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p8lout p7lout - - p3hout p3lout p2hout p2lout p8lin p7lin - - p3hin p3lin p2hin p2lin rw rw rw rw rw rw rw rw rw rw rw rw 1514131211109876543210 --------p8linp7lin-p4linp3hinp3linp2hinp2lin rw rw rw rw rw rw rw bit name function pxlin 0 1 port x low byte input level selection pins p2.7...p2.0 switch on standard ttl input levels pins p2.7...p2.0 switch on special threshold input levels pxhin port x high byte input level selection p4lin port 4 input level selection added on st10f269 pxlout 0 1 port x low byte output driver characteristic selection pins px.7...0 output driver strength is reduced after reaching vol or voh pins px.7...0 output drive is not reduced after reaching vol or voh only for st10f168 pxhout 0 1 port x high byte output driver characteristic selection pins px.15...8 output driver strength is reduced after reaching vol or voh pins px.15...8 output drive is not reduced after reaching vol or voh only for st10f168
AN1313 - application note 10/16 4.2 - wdtcon register some bits have been added for the st10f269. each of the different reset sources is indicated in the wdtcon register of the st10f269. the indicated bits are cleared with the einit instruction. it is thus possible to identify the reset during the initialization phase. st10f168: wdtcon (ffaeh / d7h) sfr reset value: 000xh st10f269: wdtcon (ffaeh / d7h) sfr reset value: 000xh note: more than one reset indication flag may be set. after einit, all flags are cleared. power-on is detected when the internal voltage rises from 0v to a value > 2.0v is recognized. 4.2.1 - hardware impacts none. 4.2.2 - software impacts none if the st10f168 software was masking the non-implemented bits. 1514131211109876543210 wdtrel ------ wdtr wdtin rw rrw 1514131211109876543210 wdtrel - - ponr lhwr shwr swr wdtr wdtin rw rrrrrrw bit function wdtin 0 1 watchdog timer input frequency selection input frequency is f cpu / 2 input frequency is f cpu / 128 wdtr watchdog timer reset indication flag set by the watchdog timer on an overflow. cleared by a hardware reset or by the srvwdt instruction. swr 1) software reset indication flag set by the srst execution. cleared by the einit instruction. new shwr 1) short hardware reset indication flag set by the input rstin. cleared by the einit instruction. new lhwr 1) long hardware reset indication flag set by the input rstin. cleared by the einit instruction. new ponr 1)2) power-on (asynchronous) reset indication flag set by the input rstin if a power-on condition has been detected. cleared by the einit instruction. new wdtrel watchdog timer reload value (for the high byte)
AN1313 - application note 11/16 5 - new registers 5.1 - new registers impacting the application this section presents new registers that have to be considered when porting an application running on the st10f168 onto the st10f269. 5.1.1 - xpercon register the st10f269 has a new register named xpercon that allows the xbus peripherals to be separately selected for being visible to the user by means of corresponding bits. if not selected (not activated with a bit of xpercon) before the xpen bit in syscon is set, the corresponding address space, port pins and interrupts are not occupied by the peripheral, and thus this peripheral is not visible and not available. st10f269: xpercon (f024h / 12h) esfr reset value: 0005h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -----------rtcenxram2enxram1encan2encan1en rw rw rw rw rw table 3 : xpercon register bits bit number bit name function reset value 0 can1en 0 1 can1 enable bit accesses to the on-chip can1 xperipheral and its functions are dis- abled (p4.5 and p4.6 pins can be used as general purpose ios, but address range 00ee00h -00efffh is only directed to external memory if can2en is 0 also.) the on-chip can1 xperipheral is enabled and can be accessed. 1 1 can2en 0 1 can2 enable bit accesses to the on-chip can2 xperipheral and its functions are dis- abled (p4.5 and p4.6 pins can be used as general purpose ios, but address range 00ee00h -00efffh is only directed to external memory if can1en is 0 also.) the on-chip can2 xperipheral is enabled and can be accessed. 0 2 xram1en 0 1 xram1 enable bit accesses to the on-chip 2kbyte xram are disabled, external access performed. the on-chip 2kbyte xram is enabled and can be accessed. 1 3 xram2en 0 1 xram2 enable bit accesses to the on-chip 8kbyte xram are disabled, external access performed. the on-chip 8kbyte xram is enabled and can be accessed. 0 4 rtcen 0 1 rtc enable bit accesses to the on-chip real time clock are disabled, external access performed. address range 00ec00h-00efffh is only directed to exter- nal memory if can1en and can2en are 0 also. the on-chip real time clock is enabled and can be accessed. 0 5...15 reserved
AN1313 - application note 12/16 5.1.1.1 - hardware impacts none. 5.1.1.2 - software impacts the value has to be changed from its default reset one to match xram size compatibility. refer to xram section for more details. 5.1.2 - poconx registers these are new registers of the st10f269. the port output control registers poconx allow to select the port output driver characteristics of a port. the aim of these selections is to adapt the output drivers to the applications requirements, and to improve the emi behavior of the device. two characteristics may be selected: C e dge characteristic defines the rise/fall time for the respective output, i.e. the transition time. slow edge reduce the peak currents that are sunk/sourced when changing the voltage level of an external capacitive load. for a bus interface or pins that are changing at frequency higher than 1mhz, however, fast edges may still be required. C dr iver characteristic defines either the general driving capability of the respective driver, or if the driver strength is reduced after the target output level has been reached or not. reducing the driver strength increases the outputs internal resistance, which attenuates noise that is imported via the output line. for driving leds or power transistors, however, a stable high output current may still be required. poconx esfr reset value: 0000h the new registers are the following: C pocon0l, pocon0h, pocon1l, pocon1h, pocon2, pocon3, pocon4, pocon5, pocon6, pocon7 and pocon8 dealing with the respective ports, C pocon20 dealing with the dedicated pins ale, rd and wr. 5.1.2.1 - hardware impacts st10f168 and st10f269 ports dont have the same behavior in their default reset configuration. the st10f269 default reset values select the fast edge mode and the high current mode, while the st10f168 is designed for fast edge mode and dynamic current mode. 1514131211109876543210 pnzdc pnzec pnydc pnyec pnxec pnxec pnwec pnwec rw rw rw rw rw rw rw rw table 4 : poconx registers bits bit function reset value pnxec 00 01 10 11 port nibble x edge characteristic (rise/fall time) fast edge mode, rise/fall times depend on the drivers dimensioning. slow edge mode, rise/fall times ~60 ns reserved reserved 00 pnxdc 00 01 10 11 port nibble x driver characteristic (output current) high current mode: driver always operates with maximum strength. dynamic current mode: driver strength is reduced after the target level has been reached. low current mode: driver always operates with reduced strength. reserved 00
AN1313 - application note 13/16 5.1.2.2 - software impacts to have on the st10f269 a behavior equivalent to the st10f168s one, poconx values must be set to the following: C 0x0044h for pocon0l, pocon0h, pocon1l, pocon1h, pocon4, pocon5, pocon6, pocon7, pocon8 and pocon20, C 0x4444h for pocon2 and pocon3. 5.2 - new registers not impacting the application 5.2.1 - odp4 register (f1cah / e5h) this is a new register of the st10f269. for can configuration support, port 4 has a new open drain function controlled with this register. 5.2.2 - exisel register (f1dah / dah) this register, standing for external interrupt source selection, has been added in the st10f269. the purpose of this new register is to select the interrupt sources of the fast external interrupts among the other peripherals. for example the cany controller receive signal (cany_rxd) can be used to interrupt the system (y = 1,2).
AN1313 - application note 14/16 6 - electrical characteristics 6.1 - dc characteristics 6.1.1 - absolute maximum ratings they are the same. 6.1.2 - dc characteristics 6.1.2.1 - operating voltage the st10f269 appears like a 5v device externally but operates at a lower internal voltage thanks to a voltage regulator. hardware impacts the pins 56 and 17 which were used as v dd and gnd for the st10f168. now for the st10f269, these pins are named dc1 and dc2, respectively pins 56 and 17, and are used as de-coupling pins for the internal core supply. software impacts none. 6.1.2.2 - programming voltage the st10f269 has a single voltage flash memory. hardware impacts the 12v input on the pin 84 is no longer needed. software impacts none. 6.1.2.3 - miscellaneous 6.2 - ac characteristics at 25mhz 6.2.1 - hardware impact none. 6.2.2 - software impact none. table 5 : dc characteristics differences symbol parameter st10f168 st10f269 unit minimum maximum minimum maximum hys input hysteresis (special threshold) 300 - 400 - mv i aleh ale active current - 600 - 500 a i pd power-down mode supply current - 100 - 500 a i pd2 power-down mode supply current (real time clock enabled, oscillator enabled) ---5ma i cc power supply current - 20 + 6 x f cpu - 30 + 4 x f cpu ma i id idle mode supply current - 20 + 3 x f cpu - 20 + f cpu ma
AN1313 - application note 15/16 7 - references the following internal documents were used to write this application note: C st10f269 data sheet. C st10f168 data sheet.
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